This invention relates, in general, to a method for planarizing a surface and, more particularly, to a method for stopping a surface planarization step.
In general, an integrated circuit fabrication technique produces a device having a non-planar surface topography. The non-planar surface topography may create a discontinuity in a film on the surface of the device. A subsequent film formed over the discontinuity may break during a thermally or mechanically stressful fabrication step. In addition, for a device having small feature sizes, a depth of focus of a photolithographic stepper becomes very small and a precise focus is difficult to achieve. Thus, a resolution of the photolithographic stepper is limited.
Typically, manufacturers of integrated circuit devices include a planarization step in the fabrication technique. One planarization method employed by integrated circuit manufacturers is a mechanical polishing technique. In the mechanical polishing technique, a non-planar surface is polished or etched by application of a frictional abrasive to the non-planar surface. Although a planar surface is obtained, this technique suffers from a lack of an adequate method to stop the planarization step before too much surface material is removed from the integrated circuit. Current approaches for stopping a polishing step are expensive and diminish a number of devices manufactured per unit time, commonly referred to as a throughput. Accordingly, it would be advantageous to have a low cost means for stopping a polishing step that is readily implemented in integrated circuit fabrication techniques and that allows a high throughput.